There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...

Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.

Traditional IC pattern-generation methods focus on detectingdefects at gate terminals or at interconnects. Unfortunately, a significantpopulation of defects may occur within an IC's gates, or cells.

Moore’s law has been the standard reference for semiconductor scaling. It roughly says that semiconductor design sizes, fueled by technology improvements, double every two years. Consequentially, the ...

As integrated circuits accommodate ever more transistors, the number of test vectors needed to test logic ICs rises dramatically. Design-automation companies are pursuing two design-for-test (DFT) ...

Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a ...

WILSONVILLE, Ore., May 18, 2015 -- Mentor Graphics Corp. (NASDAQ: MENT) today announced that Mellanox Technologies has standardized on the new Mentor® Tessent® Hierarchical ATPG solution to manage the ...

Low-power design and fast testing at the fab are not happy bedfellows. As Giri Podichetty of Mentor Graphics explains at Semiwiki and in a white paper, “the goal of automatic test pattern generation ...

As semiconductor devices advance in complexity and sensitivity to power fluctuations, the integration of power-aware automatic test pattern generation (ATPG) is becoming indispensable for yield and ...