Electronic Design

True-3D Chip-Layout Editor Facilitates Stacking Of Disparate Wafers

Say you wanted to create a chip in which a processor fabricated in 32-nm process rules would be combined with memory done on a 65-nm process and analog blocks fabricated at 180 nm. This leads you to ...
EDN

3-D wafer process combines benefits of Si, GaAs, InP

Semiconductor manufacturer Xanoptix (Merrimack, NH) has developed a wafer-scale process for the 3-D stacking of silicon with either GaAs or InP to make compound semiconductors. The company's Hybrid ...
ExtremeTech

TSMC Announces New System-on-Wafer Process With 3D-Stacking

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Hosted on MSN

Japanese chipmaker Rapidus begins test production of 2nm circuits — company commits to single-wafer processing ahead of 2027 mass production target

Rapidus on Friday announced that it had begun prototyping of test wafers with 2nm gate-all-around (GAA) transistor structures at its IIM-1 facility in Japan. The company confirmed that early test ...