EDN

Targeting Floating-Point Algorithms for FPGA or ASIC Deployment

Native Floating-Point HDL code generation allows you to generate VHDL or Verilog for floating-point implementation in hardware without the effort of fixed-point conversion. Native Floating-Point HDL ...
EDN

Variable-precision fixed/floating-point formats for Verilog

The folks at Fintronic USA Inc. are known for their high-speed, high accuracy Verilog simulator – Super FinSim. The high performance of this simulation engine is achieved by using a mixed compiled and ...