Chip testing has become increasingly complex due to the number of variables impacting designs – from design size and complexity, to high transistor counts on advanced technology nodes, to 2.5D/3D ...

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

Delay-inducing defects are causing increasing concern in the semiconductor industry today, particularly at the leading-edge 130- and 90- nanometer nodes. To effectively test for such defects, the ...

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...

For more than four decades, scan technology has somehow eluded the radar screen of the IC test industry. As test continues to evolve and make significant newsworthy changes, scan has maintained a ...

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...