EDN

Synopsys : Static timing tool offers a productivity boost

Synopsys, Inc. has announced that the 2007.12 release of its PrimeTime(R) suite has set a new performance standard for both static timing and signal integrity analysis, accelerating turnaround time ...
Design-Reuse

Optimizing Floorplan for STA and Timing improvement in VLSI Design Flow

Static timing analysis is a technique of computing of cell delay and interconnect delay in design (known as path delay) and comparing it against constrain (timing specific) set in SDC file. This paper ...
Semiconductor Engineering

Avoiding Pitfalls While Specifying Timing Exceptions

Timing exceptions are commonly used to meet timing goals while implementing a design. These exceptions typically cover asynchronous paths like clock domain crossings (CDC) or synchronous paths where ...
Electronic Design

Using Timing Constraints For Generating At-Speed Test Patterns

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...
Design-Reuse

IP Verification : Verifying timing of external IP key to SoC success

External intellectual property spans a broad range of technology. It can be as complex as an embedded digital signal processing (DSP) core or as primitive as a RAM instance. IP can come from an ...