Electronic Design

Simplify SoC Development With Embedded Testing

While the use of complex system-on-a-chip (SoC) designs has increased, unfortunately, that hasn't increased the time-to-market window for designers and chip manufacturers. As SoC designs become more ...
EDN

3-D bin packing algorithm proposed for SoC testing

Researchers from Mentor Graphics Corp. are proposing a more complete way to test multiple cores on a system-on-chip. At the International Test Conference, Mentor presented a paper that defines SoC ...
EDN

Design holds the key to cost-effective SOC testing

The most effective way to shorten test times is to test more of the SOC IP (intellectual-property) cores in parallel. However, for best results, the SOC design should anticipate parallel testing, and ...
Business Insider

Colovore Receives SOC 1 Type II Report

SAN JOSE, Calif., Sept. 15, 2017 /PRNewswire/ -- AuditOne Inc. announced that Colovore, Silicon Valley's premier provider of high-density colocation solutions, has received its SOC 1 Type II audit.
Business Wire

IPfolio Earns SSAE 18 SOC 2 Type I Security Certification, Assuring Clients, Partners and Auditors of Internal Security Controls

BERKELEY, Calif.--(BUSINESS WIRE)--IPfolio, provider of next-generation Intellectual Property Management solutions, announced today that it has completed and received its SSAE 18 SOC 2 Type I security ...