As the electronic design industry continues to push the limits of Moore's Law, a paradigm shift in timing analysis must be considered. The major reason for this is overly pessimistic timing analysis, ...

SAN JOSE, Calif. — Tool startup Silicon Dimensions Inc. has released an add-on to its Chip2Nite floor planner, block design and analysis offering that will let logic designers repair physical defects ...

Deftly optimizing ASIC critical paths, this tool rides atop existing cell-based flows to improve timing while leaving physical design largely undisturbed. Timing closure for ASIC design has always ...

Statistical static timing analysis (SSTA) offers a number of advantages over traditional corner based static timing analysis. Most notably, it provides a more realistic estimation of timing relative ...

The relentless march towards shrinking technology nodes has ushered in a new era of intricate semiconductor designs characterized by a proliferation of transistors. This intensifying complexity brings ...

Nearly all designs at advanced process nodes need some sort of power-saving strategy. As more designs employ advanced low-power techniques, design teams are discovering huge implementation hurdles ...

There’s an old saying that the first 90% of a task takes 90% of the schedule, and the remaining 10% takes the other 90% of the time. In chip development, design-signoff closure has become one such ...

ABSTRACT New methodologies have been developed to optimize EGR rate and injection timing in diesel engines, with the aim of minimizing fuel consumption (FC) and NOₓ engine-out emissions. The approach ...

IR-drop has always been somewhat of an issue in chip design; voltage decreases as current travels along any path with any resistance. Ohm’s Law is likely the first thing that every electrical engineer ...